Method for etching trench in manufacturing semiconductor devices
US6291315A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 1997 |
| Grant date | Sep 18, 2001 |
| Priority date | — |
| Expiry date | Jul 10, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3081
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer in which black silicon does not form during trench etching even when side rinsing is carried out during a photolithography process. In an embedded oxide film interposed between first and second semiconductor wafers of a bonded SOI wafer, the film thickness of a peripheral part thereof is made greater than a predetermined thickness Dsio so that it functions as an oxide film for etching prevention. When side rinsing is carried out in a resist coating process to form an opening in an oxide film for masking use in trench etching, the oxide film for masking use at the periphery is also etched during formation of the opening. Due to over-etching at that time, the oxide film for etching prevention is etched by a film thickness d1. During trench etching also, the oxide film for etching prevention is etched by a film thickness d2. Accordingly, if the film thickness Dsio of the oxide film for etching prevention is set to be greater than the film thickness d1+d2, because an oxide film remains at the final stage, the formation of black silicon can be prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.