Optimization of S/D annealing to minimize S/D shorts in memory array
US6291327A · kind A · utility
3Cited by
5References
5Claims
0Family size
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Key dates
| Filing date | Nov 13, 1998 |
| Grant date | Sep 18, 2001 |
| Priority date | — |
| Expiry date | Nov 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for eliminating source/drain shorting generated during the highly-doped source/drain implant steps in a standard STI process is provided. This is achieved by reducing the RTA temperature to be less than 1000.degree. C. so as to minimize enhanced doping diffusion. Further, the energy level for the highly-doped source/drain implant steps is increased so to compensate for poly depletion in the gate electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.