Semiconductor memory device with an improved layout of programmable fuses
US6291844A · kind A · utility
5Cited by
2References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 9, 1999 |
| Grant date | Sep 18, 2001 |
| Priority date | — |
| Expiry date | Apr 9, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A layout of fuses for programming a redundancy circuit in a semiconductor device is provided, wherein the fuses are aligned to form at least one straight line which corresponds to at least one alignment of a plurality of bonding pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.