Low-voltage CMOS phase-locked loop (PLL) for high-performance microprocessor clock generation
US6292061A · kind A · utility
26Cited by
3References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 1, 2000 |
| Grant date | Sep 18, 2001 |
| Priority date | — |
| Expiry date | May 1, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLL is implemented as a full differential circuit to improve the jitter performance and the operating voltage range. A process-compensated common-mode feedback is designed in the differential charge pump which together with loop filter of MOSFET capacitors maximizes the dynamic voltage range. A high-frequency divider capable of divide-mode change-on-flight is developed with eight divide mode programmability. A PLL start-up control circuit makes the PLL start and work under difficult conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.