Digital-to-analog interface circuit having adjustable time response
US6292122A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2000 |
| Grant date | Sep 18, 2001 |
| Priority date | — |
| Expiry date | Mar 4, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3031
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interface circuit for converting a digital signal to an analog signal. The interface circuit includes a time response adjustment circuit, a modulator, and a filter. The time response adjustment circuit receives the digital signal and generates an adjusted signal. The modulator couples to the time response adjustment circuit, receives the adjusted signal, and generates a modulator signal. The filter couples to the modulator, receives the modulator signal, and generates the analog signal. The analog signal has a time response that is modified by the time response adjustment circuit. In an embodiment, the time response adjustment circuit includes a gain element, a delay element, and a summer. The gain element receives and scales the digital signal by a scaling factor. The delay element receives and delays the digital signal by a time delay. The summer couples to the gain element and the delay element, sums the scaled signal from the gain element and the delayed signal from the delay element to generate the adjusted signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.