Method and apparatus for performing a sum-and-compare operation
US6292818A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 12, 1999 |
| Grant date | Sep 18, 2001 |
| Priority date | — |
| Expiry date | Jan 12, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/509
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sum-and-compare circuit is provided which minimizes propagation delay and which minimizes the amount of die area required to implement the sum-and-compare circuit. The sum-and-compare circuit comprises a propagate/generate logic block followed by a carry-lookahead tree structure. The propagate/generate logic block receives a first operand, A, a second operand, B, and a third operand, J. The first operand A corresponds to an addend, the second operand B corresponds to an augend, and the third operand J corresponds to the twos compliment of the constant K. The propagate/generate logic block comprises logic configured to add the operand A to the operand B to obtain a first sum and logic configured to add the first sum to the operand J to obtain a plurality of propagate signals and a plurality of generate signals, which are then output from the propagate/generate logic block to a carry-lookahead tree structure. The carry-lookahead tree structure comprises logic configured to operate on the propagate and generate signals to produce an output, Gout. The output Gout can be analyzed to determine whether the equation A+B>=K is true. The output Gout corresponds to the most significant bit …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.