Method and apparatus for reducing bus bridge thrashing by temporarily masking agent requests to allow conflicting requests to be completed
US6292865A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 1998 |
| Grant date | Sep 18, 2001 |
| Priority date | — |
| Expiry date | Jun 23, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for masking processor requests to improve bus efficiency includes a bus bridge having a detection logic for determining when a first processor on a first bus has been backed off the first bus a predetermined number of times. When the detection logic determines the first processor has been backed off the first bus the predetermined number of times, a timer is set to a first value, with the first value being sufficient to allow an agent on a second bus to access the first bus. A masking logic, coupled to the detection logic and the timer, is for masking requests from the first processor until the timer expires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.