Error detection scheme for a high-speed data channel
US6292911A · kind A · utility
29Cited by
5References
34Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 17, 1998 |
| Grant date | Sep 18, 2001 |
| Priority date | — |
| Expiry date | Dec 17, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for detecting error when transferring data on a data channel between components disposed on the data channel. A test pattern is generated by a controller on the data channel and sent to a data storage component on the channel. The data storage component tests the received test pattern to determine if the pattern has been corrupted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.