Semiconductor device with high integration density and improved performance

US6294422A · kind A · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Kazumasa Sunouchi · Yokohama, JP
• Masami Aoki · Hiratsuka, JP

Key dates

• Filing date: Dec 21, 1999
• Grant date: Sep 25, 2001
• Expiry date: Dec 21, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/033

Abstract

In a stack type memory cell of 8F.sup.2, bit line plug electrodes for connecting bit lines to source/drain diffusion layers of active regions in an area between two word lines WL are formed extend from the source/drain diffusion layers in parallel to the word lines WL and formed longer than the minimum element isolation width F and shorter than three times the minimum element isolation width F. Thus, a DRAM which uses stack type memory cells and whose integration density can be easily enhanced can be attained.