Method for fabricating a semiconductor device
US6294424A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 1999 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Oct 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/373
Abstract
The method involves forming a N well over a cell part and a P well over a periphery part of the semiconductor substrate, etching the N well and the P well to form trenches for a storage electrode and an element isolating film, forming an insulating film over the resulting structure, thereby filling the trench on the periphery part, sequentially forming a dielectric layer pattern and a storage electrode on the trench of the cell part, forming a storage electrode, forming an intermediate layer over the resulting structure, exposing the storage electrode, forming an undoped polysilicon layer over the resulting structure, thereby connecting the undoped polysilicon layer with the storage electrode, forming a polysilicon layer pattern and an intermediate insulating pattern, and forming a MOS transistor and a bit line over the polysilicon layer pattern of the cell part and the periphery part. This method is capable of decreasing the number of process and the step coverage between a cell part and a periphery part of a semiconductor substrate, thereby improving the characteristic and reliance of the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.