Plasma surface treatment method for forming patterned TEOS based silicon oxide layer with reliable via and interconnection formed therethrough
US6294476A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2000 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Oct 2, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76804
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a silicon oxide dielectric layer, where the silicon oxide dielectric layer is formed through use of a plasma enhanced chemical vapor deposition (PECVD) method employing tetra-ethyl-ortho-silicate (TEOS) as a silicon source material. There is then treated the silicon oxide dielectric layer with a plasma to form a plasma treated silicon oxide dielectric layer. Finally, there is then formed upon the plasma treated silicon oxide dielectric layer a patterned photoresist layer employed in defining the location of a via to be formed through the plasma treated silicon oxide dielectric layer. Through use of the method, the patterned photoresist layer is less susceptible to delamination from the plasma treated silicon oxide dielectric layer within an isotropic etch method employed in etching the plasma treated silicon oxide dielectric layer than is an otherwise equivalent patterned photoresist layer from an otherwise equivalent silicon oxide dielectric layer absent the plasma tr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.