Apparatus for multichip packaging
US6294731A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2000 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Mar 16, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/368
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention comprises a high performance single chip or multi-chip package which combines a CTE controlled electronic substrate, a multi-layer interconnect, bare dice or packaged devices, a top layer encapsulant and an interposer to provide a compliant and de-mountable connection to a printed circuit board. The CTE controlled electronic substrate comprises a metal or composite shell around an encapsulated core holding vertical electrical conductors. The vertical connection comprises an array of stranded or braided electrical conductors which may be exposed on the top and or bottom of the electronic substrate to provide a de-mountable interface. An interconnect layer may be attached to the planar CTE controlled electronic substrate using an adhesive or polymer. Following the connection of the interconnect to the substrate, the bare dice and/or package may be attached to the interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.