Programmable logic device with highly routable interconnect
US6294928A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 1997 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Apr 3, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device architecture with a highly routable programmable interconnect structure. The arrangement of the logic array blocks (LABs), programmable interconnect structure, and other logical elements forms a Clos network. After specific constraints have been met, the architecture is guaranteed to route. The architecture is provably routable when there is no fan-out in the middle stage. A LAB (A-200) comprises an input multiplexer region (A-504), logic elements (A-300), input-output pins (A-516), and output multiplexer region (A-508). Furthermore, a logic device and a method of operating a logic device. The device includes logic elements (B-240) that perform desired logic functions and routing functions. The logic elements (B-240) are arranged in larger logic blocks known as logic array blocks (B-230) that have local interconnection systems. The logic array blocks (B-230) are configured to provide global interconnections. The configuration provides a Clos network, whereby a signal may be routed from any input to any output without blocking.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.