Method and apparatus for low power differential signaling to reduce power
US6294933A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2000 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Feb 1, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low power differential signaling technique for reducing power in CMOS circuits. An input signal is provided to the input of a transmitter which uses transitions of the input signal to switch between two complementary resistive paths between upper and lower voltages across a common resistive element to develop a differential signal pair. In particular, during a high transition, a first pair of resistive switches are coupled across the common resistor causing current flow in a first direction and, during a low transition of the input signal, a second pair of resistive switches are coupled across the same common resistive element to cause current to flow in the opposite direction. The switching action converts a single-ended input signal to a differential signal pair across the common resistive element. The voltage swing across the differential signal pair is reduced to less than one half of the voltage differential between the upper and lower voltages which represent the source voltages. A receiver converts the differential signal pair back to a single-ended output voltage signal. The conversion of the single-ended input signal to a differential signal pair with a reduced voltage s…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.