Adaptive dead time control for switching circuits
US6294954A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 11, 2000 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Jan 11, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018585
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Apparatus for adaptively reducing dead time in a switching circuit includes overlap detection circuitry for measuring the dead time/overlap of the switches, and control circuitry for setting the dead time to the optimum level (generally the minimum possible dead time without any overlap occurring). The dead time/overlap may be detected by measuring the current through the switches, the current into the power supply, the voltage waveform at the switch point, or the average voltage waveform at the switch point. The dead time may be controlled by utilizing delay elements prior to the drivers, or by utilizing circuitry to control the driver timing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.