Non-volatile semiconductor memory device
US6295227A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 1999 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Nov 24, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided a NAND type EEPROM capable of setting a plurality of erase blocks in a single NAND cell block. The NAND cell block of a memory cell array comprises a NAND cell comprising a plurality of memory cell transistors connected in series between a bit line and a source line. Between the bit line and source line of the NAND cell, a selecting transistor is provided. A block dividing selecting transistor is provided between adjacent two memory transistors in the NAND cell, so that the NAND cell block is divided into two memory cell units. One of these memory cell units is selected as an erase unit to carry out the batch erase of data every erase unit and the write of data every page.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.