Symmetric flow control for ethernet full duplex buffered repeater
US6295281A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 1997 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | May 16, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/29
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Symmetric flow control in a buffered repeater having responsiveness to flow control frames. An Ethernet full duplex buffered repeater according to the present invention includes an internal arbitration mechanism allowing receive FIFOs of respective receive ports to transmit data over a local bus to remaining transmit ports in round-robin fashion. The transmit ports take the transmitted data off the local bus and transmit it over the respective link. Each transmit port monitors the capacity of an associated transmit FIFO, and when the available capacity falls below that required to store a maximum size frame, asserts an open collector output signal monitored by each of the ports. No port initiates transmission of a packet over the local bus when this signal is asserted. Rather than one of the transmit ports risking being unable to store a complete frame once transmission has begun, the local bus is suspended before the next frame is put on the local bus. As the receive FIFOs fill, Pause Frames are issued by the respective port over each associated link. Each port is responsive to received flow control frames for pausing transmission of data over the respective link. Each buffered re…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.