Method and apparatus for assuring cache coherency
US6295581A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 20, 1998 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Feb 20, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Access to memory is facilitated by a cache memory access system that includes individual buffers for storing and processing data access commands asynchronously, while also assuring data coherency and avoiding deadlock. Data access commands are placed in discrete buffers, in dependence upon their type: read and write to and from a client process, fill from memory, and flush to memory. To maintain data coherency, the read and write commands are processed substantially sequentially. To optimize memory access, fills are processed as soon as they are submitted, and flushes may be given lower priority than fills. To avoid deadlock, fills are generated so as to be independent of all other commands. The use of discrete buffers for cache memory access is particularly well suited to pipeline processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.