Apparatus and method for improved vector processing to support extended-length integer arithmetic
US6295597A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 1998 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Aug 11, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/386
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and a method for extended-precision vector arithmetic capable of extremely long precision (i.e., precision to as many bits as a user desires or is limited to due to memory, disk-storage, or other resource constraints). Vector carry-out bits can be used as vector carry-in bits for successive operations. In performing add or subtract operations on integers that are longer than the word size of the computer, the operands a broken into word-sized parts which are used as operands. A vector of long-integer numbers is thus broken into a series of sub-vectors, each having word-sized elements. Vector add or subtract operations are performed successively on the sub-vectors, starting with the lowest-order sub-vectors. Carry-out (or borrow-out) bits from a first vector operation are used as carry-in (or borrow-in) bits for a successive vector operation. In one embodiment, instructions are added to the instruction set of a vector processor to assist in propagating carry (or borrow) bits between components of long operands, and to assist users in accessing and controlling the carry (or borrow) bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.