Apparatus for estimating bit error rate by sampling in WDM communication system
US6295614A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2000 |
| Grant date | Sep 25, 2001 |
| Priority date | — |
| Expiry date | Mar 2, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/203
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A sampling system for estimating the bit error rate of a signal carried by a communication system is provided. The sampling system includes an optical transmission medium for carrying an optical signal. A clock regenerator circuit is connected to the optical transmission medium. The clock regenerator circuit receives the optical signal and generates a synchronous clock signal. A clock divider circuit receives the synchronous clock signal and produces a divided clock signal. A sampling circuit receives a divided clock signal and produces a digitized signal. A threshold determination circuit compares the digitized circuit to a predetermined threshold value. The threshold determination circuit also produces an indicator signal representing the logic value of the digitized signal. In order to estimate the bit error rate, a histogram processor receives the digitized signal and the indicator signal, and generates a histogram representing statistical information about the optical signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.