Evaluation circuit for electronic signal transmitters
US6297673A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 17, 1999 |
| Grant date | Oct 2, 2001 |
| Priority date | — |
| Expiry date | Nov 17, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/262
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The evaluation circuit has a current interface (1,1'; 11,11') for a current signal (i.sub.2) from an electronic signal transducer (6,6'; 16,16'); a current-sensing FET (3,3'; 13,13') having a gate (G), a source (S), a drain (D) and a sensing output (sense), which is connected so that the current signal from the transducer passes through the source and drain; a monitoring circuit (5,5'; 15,15') for controlling the current-sensing FET in the event of a malfunction connected between the gate (G) and to the drain (D) or source (S); a current reflector circuit (4,4'; 14,14') having an input connected to the sensing output (sense) of the current-sensing FET and a resistor (2,2'; 12,12') for converting current to voltage, which is connected to an output of the current reflector circuit, so that the current signal is converted to a voltage signal tapped between the resistor and the current reflector circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.