Patent · US Expired

Coherent variable length reads from system memory

US6298420A · kind A · utility

13Cited by

12References

2Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Suresh Chittor · Beaverton, US
Chih-Cheh Chen · Hillsboro, US
Sin S. Tan · Portland, US
Jonathan Spitz · Leonberg, DE

Key dates

Filing date	May 8, 2000
Grant date	Oct 2, 2001
Priority date	—
Expiry date	May 8, 2020

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/0886
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Method and apparatus for processing serial bus read requests in a memory controller when the memory controller interfaces to both a pipelined bus and a serial bus. According to the method, the read request message is received and is split into several atomic transactions. The atomic transactions are issued on the pipelined bus. Data related to the several atomic transactions is stored in a queue. The requested data is read from the queue and placed in a response message on the serial bus.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.