Interconnect minimization in processor design
US6298471A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 20, 1999 |
| Grant date | Oct 2, 2001 |
| Priority date | — |
| Expiry date | Aug 20, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are described for optimizing interconnections between busses and function units and registers. The method includes identifying each bus in a plurality of busses and at least one hardware component to which each bus is assigned for a given operation. At least two bus assignments are identified for which different operations occur on the same hardware component. Hardware components are assigned for different operations occurring on the same hardware component to the same bus. The optimization process can be efficiently carried out using conventional algorithms for solving assignment problems. Use of these assignment problem algorithms provides an efficient and reliable way of optimizing the bus assignments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.