Isolated flip chip or BGA to minimize interconnect stress due to thermal mismatch
US6299053A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 1999 |
| Grant date | Oct 9, 2001 |
| Priority date | — |
| Expiry date | Aug 16, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10734
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A wiring substrate with reduced thermal expansion stress. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or ball grid array package. The wiring substrate has a thermal expansion stress reduction insert, void, or constructive void in a thermal expansion stress region proximate to the integrated circuit. The thermal expansion stress reduction insert or void may extend a selected distance from the edge or edges of the integrated circuit attachment area. The thermal expansion stress reduction insert or void improves the flexibility of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly. In another embodiment, layers of a laminated wiring substrate are intentionally not bonded beneath the chip attach area, thus allowing greater flexibility of the upper layer of the laminate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.