Silicon interconnect passivation and metallization process optimized to maximize reflectance
US6300241A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 1998 |
| Grant date | Oct 9, 2001 |
| Priority date | — |
| Expiry date | Aug 19, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2201/123
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A metal surface having optimized reflectance is created utilizing the following process steps alone or in combination: 1) CMP of dielectric layer underlying the metal following SOG planarization; 2) CMP of dielectric layer underlying the metal following formation of vias; 3) forming a metal adhesion layer composed of collimated titanium over the underlying dielectric; 4) depositing metal upon the adhesion layer at as low a temperature as feasible to maintain small grain size; 5) depositing at least the first layer of the reflectance enhancing coating on top of the freshly deposited metal prior to etching the metal; and 6) depositing the initial layer of the reflective enhancing coating at a temperature as close as possible to the temperature of formation of the metal electrode layer in order to suppress hillock formation in the metal. Deposition of the REC serves two distinct purposes. First, the REC coats the freshly deposited metal layer immediately following deposition, preserving the metal in its highly reflective state. Second, the REC generates constructive interference of light reflected by the metal layer. This constructive interference can generate reflectivity greater tha…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.