System, IC chip, on-chip test structure, and corresponding method for modeling one or more target interconnect capacitances
US6300765A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 9, 1999 |
| Grant date | Oct 9, 2001 |
| Priority date | — |
| Expiry date | Feb 9, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2884
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system, an IC chip, a test structure formed on the IC chip, and a corresponding method for modeling one or more target interconnect capacitances is disclosed. The test structure comprises an interconnect configuration comprising a test interconnect and one or more target interconnects. The interconnect configuration has, for each target interconnect, a corresponding target interconnect capacitance between the test interconnect and the target interconnect. The test structure also comprises a test interconnect charging circuit connected to the test interconnect. The test interconnect charging circuit is configured to place a test charge on the test interconnect. The test structure further comprises one or more target interconnect charging circuits. Each target interconnect charging circuit is connected to a corresponding target interconnect. Each target interconnect charging circuit is configured to draw a target interconnect charging current from the corresponding target interconnect in response to the test charge. This places an opposite charge on the corresponding target interconnect that is induced by the corresponding target interconnect capacitance. As a result, a measurement…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.