Integrated circuit I/O buffer with series P-channel and floating well
US6300800A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 1999 |
| Grant date | Oct 9, 2001 |
| Priority date | — |
| Expiry date | Nov 24, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09429
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit output buffer includes a core terminal, a pad terminal, a pad pull-up transistor, a pad pull-down transistor, a pull-up voltage protection transistor, and a selectively conductive pad voltage feedback path. The pad pull-up transistor and the pad pull-down transistor are coupled to the pad terminal and are biased to respectively charge and discharge the pad terminal in response to a data signal received on the core terminal. The pull-up voltage protection transistor is coupled in series between the pad pull-up transistor and the pad terminal and has a control terminal and a well terminal. The selectively conductive pad voltage feedback path is coupled between the pad terminal and the well terminal of the pull-up voltage protection transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.