Scanning circuit for driving liquid crystal display
US6300928A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 9, 1998 |
| Grant date | Oct 9, 2001 |
| Priority date | — |
| Expiry date | Jul 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A scanning circuit that can minimize the number of input signals and switch signals applied to row lines of a liquid crystal panel, and reduce deterioration of a circuit is disclosed. The circuit includes input signal lines and a plurality of substantially identical stages cascade-connected to the input signal lines to produce a plurality of phase delayed scanning signals. Each stage has an input terminal and an output terminal. Also, each stage is provided with output circuitry comprising a push-pull amplifier including pull-up and pull-down transistors having respective conduction paths connected in series with the output terminal thereof and respective control electrodes, the push-pull amplifier having a supply terminal for applying one of the phase delayed scanning signals, input circuitry responsive to scanning pulse applied to the input terminal for generating first and second control signals which are coupled to the control electrodes of the pull-up and pull-down transistors for conditioning the push-pull amplifier to provide output scanning pulses, and means for raising a voltage of the first control signal to be applied to the control electrode of the pull-up transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.