Static random access memory (RAM) systems and storage cell for same
US6301146A · kind A · utility
Inventors
Key dates
| Filing date | Dec 23, 1999 |
| Grant date | Oct 9, 2001 |
| Priority date | — |
| Expiry date | Dec 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of continuously replenishing a four-transistor static RAM storage cell is described. Such method comprises biasing both the back gate terminals and the normal gate terminals of the two bit line coupling transistors in the static RAM storage cell to voltage levels for causing a flow of small compensating currents through such coupling transistors when they are in a standby or non-access condition. Such small compensating currents are supplied to the two storage transistors in the storage cell for replenishing leakage of charge from the parasitic capacitance in the storage cell. The bias voltages arc supplied by adaptive bias circuits which adjust the bias voltages to track changes in the leakage of charge from the parasitic cell capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.