Nonvolatile semiconductor memory device
US6301153A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2000 |
| Grant date | Oct 9, 2001 |
| Priority date | — |
| Expiry date | Feb 23, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/344
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell array includes first and second memory cell groups which are simultaneously selected at the time of erasing. A first bit line is connected to the first memory cell group and a second bit line is connected to the second memory cell group. The first and second bit lines are commonly connected to a data circuit having a latch circuit. First data read from the first memory cell group at the time of erase verify read for the first memory cell group is input to the data circuit and second data read from the second memory cell group at the time of erase verify read for the second memory cell group is input to the data circuit. The data circuit latches data indicating that the erasing operation is completed into the latch circuit when both of the first and second data items indicate that the erasing states of the memory cells are sufficient and latches data indicating that the erasing operation is effected again into the latch circuit when at least one of the first and second data items indicates that the erasing state of the memory cell is insufficient.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.