Memory controller for an ATSC video decoder
US6301299A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 1998 |
| Grant date | Oct 9, 2001 |
| Priority date | — |
| Expiry date | May 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/13
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A video memory system for storing ATSC video image data is configured as three channels, each channel having two banks and each bank including a plurality of memory rows. The exemplary memory system includes a buffer area for holding bit-stream data and six field buffer areas. The field buffer areas are arranged in pairs to form a three frame buffer areas, such that the buffer areas for the two fields in a given frame are allocated in respectively different banks. The video memory system includes an output memory controller which receives macroblocks of decoded image data and divides the received macroblocks into respective upper and lower half-macroblocks, the upper half-macroblock being stored in one field buffer of the frame and the lower half-macroblock being stored in the other field buffer of the frame. In addition, the output memory controller stores the luminance and chrominance components of the half-macroblocks in respectively different channels of the memory device and the channel assignment is changed from one half-macroblock to the next. The memory system also includes an input memory controller which retrieves reference half-macroblocks from the memory. The input memo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.