High speed/low speed interface with prediction cache
US6301629A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 1998 |
| Grant date | Oct 9, 2001 |
| Priority date | — |
| Expiry date | Mar 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a monolithic or discrete high speed/low speed interface that is capable of interfacing with the high speed subsystems of a data processing system and low speed subsystems of a data processing system. In one embodiment, the high speed/low speed interface subsystem of the present invention comprises a high speed interface for interfacing with high speed subsystems via a high speed bus, a low speed interface for interfacing with low speed subsystems via a low speed bus, a control circuitry coupled to both the high speed and low speed interfaces, and an internal bus coupled to the control circuitry and the high speed and low speed interfaces. The control circuitry controls the transfer of information between the interfaces. In a second embodiment of the present invention, the high speed/low speed interface subsystem of the present invention comprises all the elements of the first embodiment and a prediction unit. In a third embodiment of the present invention, the high speed/low speed interface subsystem comprises all the elements of the second embodiment and a memory controller. The embodiments of the present invention could be implemented with discrete …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.