Content addressable memory system with cascaded memories and self timed signals
US6301636A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2000 |
| Grant date | Oct 9, 2001 |
| Priority date | — |
| Expiry date | May 18, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes cascaded content addressable memory (CAM) chips connected to a common bus. Each CAM chip includes a CAM array, a self-timed signal generator and hit propagation and match address transfer circuits. Each CAM array including an array of core cells provides, through its encoder, hit and match address signals resulting from a search operation in response to a clock signal. Each match address transfer circuit transfers the match address signal to the common bus, in response to a self-timed signal, the hit signal and a propagation-in hit signal provided from an upstream CAM chip, so that more than one CAM chip is prevented from providing the match address signal to the common bus simultaneously. Each hit propagation circuit provides a propagation-out hit signal to a downstream CAM chip, in response to the self-timed signal, the hit signal and the propagation-in hit signal from the upstream CAM chip, so that a hit signal is propagated from an upstream CAM chip to a downstream CAM chip. Each CAM chip may include an extra row for providing a modelmiss signal or a modelhit signal which is used for a generating self-timed signal. Each word may be divided into two halves and …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.