Method for reducing the frequency of cache misses in a computer
US6301641A · kind A · utility
9Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1998 |
| Grant date | Oct 9, 2001 |
| Priority date | — |
| Expiry date | Feb 27, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99932
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A score is computed of how many cache misses occur for the execution of each of a number of blocks. The score is used as a heuristic in a local search in which an original selection is iteratively replaced each time by a selection that differs from the original selection only by the movement of a single block and that has a lower number of cache misses for the sample of execution than the original selection. Thus a selection of locations for placing instructions of a program in main memory is found that minimizes the number of cache misses that occur for a sample of a typical execution of the program.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.