Exception processing in asynchronous processor
US6301655A · kind A · utility
31Cited by
2References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1998 |
| Grant date | Oct 9, 2001 |
| Priority date | — |
| Expiry date | Sep 15, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Exception handling systems and techniques for handling exceptions and sequencing conflicts in an asynchronous processor. Two designated queues are used to respectively keep program counter values of instructions and the assignments of the execution units for executing the instructions according to the program order. An asynchronous circuit is coupled between the program counter unit and the write-back unit of the processor to provide asynchronous communications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.