Security methodology for devices having plug and play capabilities
US6301665A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1998 |
| Grant date | Oct 9, 2001 |
| Priority date | — |
| Expiry date | Apr 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A security methodology and security logic for protecting Plug and Play computer system components from unauthorized access. The security logic prevents modification of the base addresses of specified Plug and Play computer system components by blocking writes to specific index locations programmed into security registers. In the disclosed embodiment of the invention, the base address of a Super I/O chip is protected, as well as the base addresses of specified logical devices in the Super I/O chip. Protecting the base addresses in this manner prevents the security logic from being circumvented by interfering with the address decoding used to track reads and writes to protected index registers. In addition, the security registers are programmed to prevent access to the protected index registers of the logical devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.