Insertion of test points in RTL designs
US6301688A · kind A · utility
33Cited by
8References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 24, 1998 |
| Grant date | Oct 9, 2001 |
| Priority date | — |
| Expiry date | Nov 24, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318378
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method is disclosed for inserting test points in RTL VHDL designs or other high level circuit designs such that after a synthesis process the resulting gate-level design contains test points which improves fault coverage in a Full Scan BIST environment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.