Method to improve integrated circuit defect limited yield

US6301690A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Gary S. Ditlow · Garrison, US
• Daria R. Dooling · Waterbury, US
• David E. Moran · South Burlington, US
• Richard L. Moore · Princeton, US
• Gustavo E. Tellez · South Burlington, US
• Ralph J. Williams · South Burlington, US
• Thomas Wood Wilkins · Shelburne, US

Key dates

• Filing date: Jul 12, 1999
• Grant date: Oct 9, 2001
• Expiry date: Jul 12, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3011
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for manufacturing an integrated circuit having improved defect-limited yield. Each conductor on the integrated circuit is represented as an electrical element of a network, having branch voltages and currents. The width of the conductor is advantageously selected to have the minimum width necessary to produce signal levels that have sufficient noise margins. An integrated circuit conductive grid is thus realized having a reduced cross sectional area along a portion of various conductor element lengths, to reduce the risk that particles produced during manufacturing will result in bridging of adjacent conductor elements.