Pad layout and lead layout in semiconductor device
US6303948A · kind A · utility
7Cited by
5References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1997 |
| Grant date | Oct 16, 2001 |
| Priority date | — |
| Expiry date | Feb 26, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor chip and a circuit formed in the semiconductor chip. Pads are arranged in a plurality of rows on the semiconductor chip and electrically connected to the circuit. The pads on adjacent rows are offset from each other. Leads are provided on the semiconductor chip and bonding wires selectively connect the leads to the pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.