Semiconductor chips encapsulated within a preformed sub-assembly
US6303974A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 1998 |
| Grant date | Oct 16, 2001 |
| Priority date | — |
| Expiry date | Dec 7, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a housing of a semiconductor device there are provided a plurality of semiconductor chips captivated in a preformed sub-assembly and arranged to present contact areas for connection to anode and emitter electrodes of the semiconductor housing. Electrically conductive contact pin arrangements project from electrically insulated channels in the preformed sub-assembly, an inward end of each of the pin arrangements being so arranged, when urged into its channel, as to provide an electrical connection to a part of the surface of a semiconductor chip. There is a sheet of electrically conductive material, resting on a base level of an inner surface of the emitter electrode and electrically isolated therefrom by an electrically insulating insert, as a means for distributing an electrical signal and making simultaneous contact with the opposite ends of the pin arrangements. The channels and the pin arrangements are such that the pin arrangements are out of contact with the semiconductor chips when the preformed sub-assembly is not supported on a surface which interacts with the opposite ends of the pin arrangements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.