Phase detector that samples a read signal at sampling points and delay
US6304071A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 1999 |
| Grant date | Oct 16, 2001 |
| Priority date | — |
| Expiry date | Jan 6, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0334
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A phase detector determines a phase error value dependent on the relative phase between a local oscillator signal, used for the system clock, and an input signal received over a PR (a, b, b, a) channel. The error value is used to lock the phase and frequency of an input signal to the phase and frequency of the clock in a phase-lock loop (FIG. 1, not shown). The input signal is sampled at regular intervals in accordance with the local oscillator signal, and the sampled values provided on a line 10. A threshold slicer 22 selects an ideal sample value for a sampling point by comparing the sampled values with thresholds received on threshold inputs 23 to 26. A subtracter 32 determines a difference value which corresponds to a difference between the ideal sample value and the actual sample value for that sampling point. A subtracter 28 and a delay register 29 operate to determine the sense of change to the ideal sample value from a ideal sample value for a preceding sampling point. A second subtracter 42 and a second delay register 31 determine the sense of change to the ideal sample value for a preceding sampling point from a ideal sample value for a twice preceding sampling point. The…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.