Bias circuit for depletion mode field-effect transistors
US6304130A · kind A · utility
11Cited by
6References
41Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1999 |
| Grant date | Oct 16, 2001 |
| Priority date | — |
| Expiry date | Dec 23, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/301
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a bias circuit for biasing a depletion mode power transistor. The bias circuit includes a voltage offset circuit and a transistor, where the voltage offset circuit is serially coupled between the gate terminal of the depletion mode power transistor and the drain terminal of the transistor. The bias circuit generates a bias voltage that, when applied to the gate terminal of the depletion mode power transistor, maintains a substantially constant drain current through the power transistor over a range of threshold voltages caused by process and temperature variations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.