High power supply ripple rejection internally compensated low drop-out voltage regulator using PMOS pass device
US6304131A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2000 |
| Grant date | Oct 16, 2001 |
| Priority date | — |
| Expiry date | Feb 22, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/575
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A high power supply ripple rejection internally compensated low drop-out voltage regulator using an output PMOS pass device. The voltage regulator uses an intermediate amplifier stage configured from a common source, current mirror loaded PMOS device to replace the more conventional source follower impedance buffer associated with conventional Miller compensation techniques. Compensation is achieved through use of a small internal capacitor that provides a very low frequency dominant pole at the output of the input stage while effectively pushing out the two other poles at the outputs of the second and third gain stages to a frequency well outside of the unity gain frequency to ensure closed loop stability. High, wide bandwidth PSRR is achieved through an integrated circuit implementation of three voltage gain stages compensated by a nested active Miller compensation technique that does not impedance shunt the output series PMOS pass device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.