Delay correction system and method for a voltage channel in a sampled data measurement system
US6304202A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2000 |
| Grant date | Oct 16, 2001 |
| Priority date | — |
| Expiry date | Jan 18, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06J1/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Delay correction in a dual-channel analog-to-digital converter (ADC) is accomplished by insertion of coarse and fine delay correction registers prior to and after a frequency reduction element in a voltage channel. A dual-channel ADC includes first and second delta-sigma modulators and a digital filter, subject to multiple sampling rates for optimizing coarse and fine adjustments of delay. An energy calculation is performed in a sampled data domain, which is implemented using digital multiplication techniques in a delay compensation scheme performed in the digital domain. The digital data subject to filter processing is delayed by predetermined amounts. The dual-channel ADC is provided with a programmable channel delay adjustment in the voltage channel thereof. A delay differential equal to .DELTA.I-.DELTA.V is calibrated and compensated subject to an acceptable time delay for production of a correct energy value. The ADC according to the present invention further oversamples received analog signal at clock rates much higher than the output rate of the ADC, and delays are generated in the downstream filters connected to the ADCs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.