Digital video camera with high-speed mode
US6304292A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jan 9, 1997 |
| Grant date | Oct 16, 2001 |
| Priority date | — |
| Expiry date | Jan 9, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N2209/046
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A digital video camera includes an addition circuit in which an offset set by a CPU is added to an output from an A/D converter. A clamp level calculation circuit calculates a clamp level on the basis of an average level of eight pixels included in each line within a back end OB (optical black) level detection area in a normal mode, or calculates a clamp level on the basis of an average level of two pixels included in each line within a front end OB level detection area in a quadruplication mode. A first subtraction circuit subtracts the clamp level from an output of the addition circuit so as to clamp the output of the addition circuit. An output of the first subtraction circuit is clipped at a zero-level by a zero-clipping circuit, and an output of the zero-clipping circuit is applied to a second subtraction circuit through a low-pass filter, whereby the same offset can be subtracted from the output of the zero-clipping circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.