Automated test vector generation and verification
US6304837A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1998 |
| Grant date | Oct 16, 2001 |
| Priority date | — |
| Expiry date | Sep 24, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318378
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed is a method for generating AVF test file data for use in testing a simulation of an integrated circuit design, and verifying the generated AVF test file data before they are delivered to a physical silicon version of the integrated circuit design. The generation method includes providing a map file that contains a plurality of identifying statements for each multiple port I/O cell (or also including single port I/O cells) in the integrated circuit design. Then, generate a verilog executable file for the integrated circuit design. The verilog executable file is configured to contain data associated with the map file, a netlist of the integrated circuit design, output enable data derived from the netlist, and AVF data conversion information. The method further comprises executing the verilog executable file along with a test bench that includes the netlist of the integrated circuit design, a set of test files, and models. The execution is configured to produce the AVF test file data and a DUT timing file data. The generated data is then processed through a verification loop that is configured to identify in a log all of the possible errors with the generated test data. The …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.