FFT-based parallel system for array processing with low latency
US6304887A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Sep 11, 1998 |
| Grant date | Oct 16, 2001 |
| Priority date | — |
| Expiry date | Sep 11, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/142
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DSP system is provided for performing FFT computations with low latency by parallel processing of complex data points through a plurality of butterfly FFT execution units. The system simplifies the circuitry required by employing a single address generator for all of the memory units coupled to like ports on each execution unit. All RAM's connected to, for example, the A ports of a plurality of DSP's will be addressed by a single address generator. Similarly, all RAM's connected to the B ports of a plurality of DSP's will be addressed by a single address generator. Simple one-port RAM memory is suitable for use with the invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.