Lifetime-sensitive instruction scheduling mechanism and method
US6305014A · kind A · utility
80Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1998 |
| Grant date | Oct 16, 2001 |
| Priority date | — |
| Expiry date | Jun 18, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction scheduler in an optimizing compiler schedules instructions in a computer program by determining the lifetimes of fixed registers in the computer program. By determining the lifetimes of fixed registers, the instruction scheduler can achieve a schedule that has a higher degree of parallelism by relaxing dependences between instructions in independent lifetimes of a fixed register so that instructions can be scheduled earlier than would otherwise be possible if those dependences were precisely honored.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.