Delay time control circuit
US6307403A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1999 |
| Grant date | Oct 23, 2001 |
| Priority date | — |
| Expiry date | Dec 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/133
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay time control circuit comprises a delay circuit composed of 2.sup.n series-connected unit delay circuits each including a pair of series-connected, first and second inverters, where n is an integer equal to or more than 2, buffer circuits each connected to an output of each of the first and second inverters of the unit delay circuits of the delay circuit, 2.sup.n-1 first connection lines each connecting between outputs of adjacent ones of the buffer circuits connected to the second inverters and 2.sup.n-2 second connection lines each connecting between adjacent ones of the first connection lines. In response to an input signal input to the first inverter of first one of the unit delay circuit, an output signal delayed with respect to the input signal is obtained through one of the first connection lines and one of the second connection lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.