Integrated circuit reset incorporating battery monitor and watchdog timer
US6307480A · kind A · utility
15Cited by
16References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 1, 1997 |
| Grant date | Oct 23, 2001 |
| Priority date | — |
| Expiry date | Aug 1, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0757
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reset circuit that incorporates a battery monitor and watchdog timer in an integrated circuit is disclosed. A battery monitor having an output indicative of a charge state of a battery and a watchdog timer having an output indicative of an operational state of software being executed by the integrated circuit are connected to reset logic having a reset signal output, wherein the reset logic generates a reset signal on the reset signal output if either the battery monitor output or the watchdog timer output is active.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.